资源列表
binary2bcd
- This build is for developing a \"binary-to-BCD\" converter for use in // displaying numerals in base-10 so that people can read and interpret the // numbers more readily than they could if the numbers were displayed in // binary or hexadecimal
DaFilter
- /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generate
Shifters_vhdl
- -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at --- Title : Barrel Shift
cf_interleaver2
- interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器, 包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料 -interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species,
fpu_v18
- <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_s
System09
- BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO
VerilogHDLICdesign
- 精通VerilogHDL：IC设计核心技术实例详解-proficient VerilogHDL : IC design example explanation of the core technology
RSSI_contr
- VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage
lcd_controlveriloghdl
- 使用Ｖeriolog hdl 编写手机屏测试程序．-Veriolog hdl prepared to use cell phone screen test.
Verilog-HDL
- 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples w
USB2.0IP_core_Verilog
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
VerilogHDLPLI
- Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,