资源列表
add_sub_lab2
- 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl descr iption, including analysis and reporting.
110detector_lab
- 一个简单的探测110三位的探测器，用逻辑图和vhdl描述，包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl descr iption, including reports and experimental test plan.
2460100Time
- 24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~
addersubtractor
- 这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
cpld1380
- 一个很好的VHDL实现的功能模块程序,希望你可以用的上!-a good VHDL functional module procedures in the hope that you can use!
KEY12
- １３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用-13 key keyboard VHDL top-level document, I was a novice with the hope that useful for beginners
DEBOUNCE
- 一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference
USB245I
- USB245I的基于FPGA的VHDL语言的驱动程序,应该有用-USB245I based FPGA VHDL of the driver, should useful
SONGER
- 基于FPGA的VHDL可以产生不同的音调,象音乐一样-based FPGA VHDL can produce different tones, like the same music
vhdl2009
- 并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through) -- The code can now achieve a single byte of Transceivers
fifo_01
- 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8 -- 8-bit Identity Comparator -- uses 1993 std VHDL --
decode_for_m68008
- -- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X\"00000\" to X\"01FFF\" -- csbar(1) : X\"40000\" to X\"43FFF\" -- csbar(2) : X\"08000\" to X\"0AFFF\" -- csbar(3) : X\"E000