资源列表
bt656_to_yuv422
- 从bt656数据流中提取出同步信号, 适合于搞fpga/cpld开发调式-bt656 internel sync to extern sync singal， bt656 internel sync to extern sync singal
cdr
- 数据时钟恢复，采样8倍率高频时钟进行数据时钟恢复。已通过Modelsim仿真-Data and clock recovery, sampling 8 times the rate of high frequency clock for clock and data recovery. Have been through the Modelsim simulation
ADC_handle
- 针对ADC器件AD9226的数据采集处理流程，针对手册时序做的有效数据输出控制。Verilog HDL- ADC AD9226 data acquisition device for processing flow for the manual timing do valid data output control.Verilog HDL
fifo_mem
- 同步FIFO，IP核生成ram，已验证可用。-Synchronous FIFO, IP core generation ram, verified available.
soft_hdmi
- 模拟adv7619 hdmi 4k视频输出信号-Analog adv7619 hdmi 4k video output signal
msk_modulation
- 用verilog硬件描述语言写的msk调制程序,可以拿来参考一下-With verilog hardware descr iption language to write msk modulation process, you can refer
add1A
- 用于实现锁相光子计数技术的累加器，verilog语言-Accumulator achieve specific cases for accumulator lock detection of photon counting technique
verilog_cordic
- 采用verilog编写的经典的cordic算法，旋转模式，亲测可用，经过了9次旋转-Classic verilog prepared by the cordic algorithm, rotation mode, pro-test available, after nine rotation
dht11
- DTH11温湿度模块的verilog HDL 代码-The verilog HDL code of DTH11
edge-detection1
- 基于FPGA开发环境，根据Sobel model算法，关于边缘检测的verilog代码。-the code of edge detection based on verilog.
led_test
- 在例程中，我们要做的是流水灯实验，顾名思义就是要LED象流水一样的点亮，这样说吧，就是先单独点亮第一个，然后点亮第二个-In the routine, we have to do is water lamp experiments, as the name suggests is to water, like the LED is lit, so to speak, a first single lighting is the first, second and lighting
FJEXW91IHWIQ3I8
- smart fan project for vhdl 5 part)(3)