资源列表
FY0JHMFIHWIQ3I7
- smart fan project for vhdl 5 part(last)
fft
- FFT implementation using fused floating point operations
radix4
- FFT implementation using fused floating point operations
dot_product
- FFT implementation using fused floating point operations
addition
- FFT implementations using fused floating point operations
E4_4_IIR4Functions
- 用verilog语言实现的一个IIR滤波器，因为现在的ise等工具中没有包含相关的ip核，所以需要手动设计。 -With verilog language to achieve an IIR filter, because now ise and other tools do not contain the relevant ip kernel, so the need for manual design.
file_test
- modeslsim仿真读写文档内容的实现以及显示操作内容的功能-Modeslsim simulation to read and write the contents of the document and display the contents of the operation of the function
simple
- FIRST WORD FALL THROUGH FIFO
n_Bit_Counter
- n bit counter verilog code
clock
- 一个简易的数字钟，可以根据输入的时钟频率来计时-A simple digital clock can be clocked based on the input clock frequency
jsq
- 一个在ise平台上写的计算机小程序，可以计算加减乘除，输入位数为10位，三位小数-A computer on the ise platform to write a small program, you can calculate the addition and subtraction multiplication and division, the input bit is 10, three decimal
seg7
- 数码管实验，包括段选位选，通过了FPGA开发板验证。-Digital tube experiments, including the election of the selected segment, through the FPGA development board validation.