资源列表
[verilog]dcfifo_256x32
- Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.
axi_master
- DDR3 控制器，axi4_full 模式， burst长度为16，应用于xilinx平台。-DDR3 interface controller， axi4_full working mode with burst length 16, can operate on the xilinx platform.
spi_master
- SPI 控制接口，可支持传输位数的动态配置。-SPI standard controller interface，can support configure dynamically.
crc_unit_16
- 用verilog语言实现CRC16校验，已通过仿真验证。-Use verilog language implementation CRC16 calibration, was validated by simulation
responder
- basys2实现抢答器，Verilog描述语言，实现4人抢答器，功能已验证-Basys2 u5B9 u73B0 u62A2 u7B54 u5668 uFF0CVerilog u63CF u8FF0 u8BED u8A09 uFF0C u5B9E u73B04 u4EBA u62A2 u7B54 u5668 uFF0C u529F u80FD u5DF2 u9A8C u8BC1
led_display
- 用硬件描述语言verilog hdl来描述led等的显示。-led display
s2p
- 用硬件描述语言verilog hdl 写的串行转并行代码。-convert serial to parallel
scan_led
- 用硬件描述语言verilog hdl写的实现动态扫描显示的代码。-Using Hardware Descr iption Language Verilog HDL written to achieve dynamic scanning display code.
Butterfly_lovers_beef
- verilog编写的蜂鸣器音乐《梁山伯与祝英台》。系统时钟为50MHz。-Verilog prepared buzzer music Butterfly Lovers . The system clock is 50MHz.
cla_16bit
- verilog 16bit carry lookahead adder-verilog 16bit carry lookahead adder
fec
- RS编码电路 ，包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
qam16 modulator
- QAM16 MODULATOR VERILOG CODE ON FPGA