资源列表
HDMI_test
- 基于fpga板子和hdmi传输 测试代码文件(hdmi test code for FPGA)
SPI_master
- spi-master模块的verilog(simple program for SPI-Master)
AD9512_coe
- AD9512 提供多路输出时钟分配功能，输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性，能够极大地提升数据转换器的时钟性能。(AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the cl
syn_dp_fifo.v
- 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
Clock generator
- A clock Generator in verilog
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
cameralinkin_2_axis
- cameralink转axi_stream接口(cameralink to axi_stream)
flash_test
- 使用Verilog HDL语言驱动FPGA读写flash(FPGA read and write flash)
KEYPD
- Keypad sample. Vhdl language
UART
- UART串口通信模块：包括接收模块RXD、发送模块TXD、分频模块FREDIV(UART serial communication module: including receiving module RXD, sending module TXD, frequency division module FREDIV)
ADC
- vhdl analog digital converter
ac_acquire
- ads127l01串联模式，串联了两个芯片，此时最大采样率不能用。osr的值为 01，10，11.(Ads127l01 series mode, in series with two chips, at this time the maximum sampling rate can not be used. The value of OSR is 01, 10, 11.)