资源列表
cu
- 用VHDL硬件描述语言编写数码管译码显示-Using VHDL hardware descr iption language decoding digital tube display
rshift1
- right shifter using vhdl,
pulse
- 实现功能简述:verilog写的 本模块主要功能是产生一个确定时钟周期长度（最长为256个时钟周期）的脉冲信号，可以自己设定脉冲长度，输出的脉冲信号与时钟上升沿同步 脉冲宽度 = pulsewide + 1 时钟周期 输入一个启动信号后，可以产生一个固定时钟周期长度的脉冲信号，与启动信号的长短无关！脉冲宽度可调！-Functional Descr iption of the module to achieve the main function is to produce a
IC61LV256-15TC
- 用vhdl实现的IC61LV256-15TC控制程序，调试已通过-Implemented using vhdl IC61LV256-15TC control procedures, testing has passed
txm
- txm 传输模块，处理并信号转成窜行信号 -txm transmission module, process, and channeling the line signal into a signal
filter_lowpass
- 基于Verilog的低通滤波器的设计与实现-Based on the Verilog low-pass filter of design and implementation
LED
- 用ATMEGA16芯片单片机实现 步进电机缓慢单向转动 -ATMEGA16 chip microcontroller stepper motor slow unidirectional rotation
collectdata_top
- 视频数据通过SAA7113芯片，转换成数字信号，数据采集verilog代码-SAA7113 data collect verilog code
pid-control-program
- pid示例程序，使用arduino单片机-pid example, the use arduino microcontroller
Key_Dis---1
- 实现键盘动态扫描，按键次数在数码管上显示，属于FPGA基础应用程序-Achieve dynamic scanning keyboard, keystrokes on the digital display, is FPGA-based applications
LCD-display-16x2-8bit
- LCD 16x2 8-bit code for atmel uc3c0512c microcontroller
exp11
- 在掌握可控脉冲发生器的基础上了解正负脉宽数控调制信号发生的原理。熟练的运用示波器观察实验箱上的探测点波形。掌握时序电路设计的基本思想。-On the basis of mastering the controllable pulse generator, the principle of the digital modulation signal of the positive and negative pulse width is understood. Skilled use of osci