资源列表
keyscan
- verilog 写的keyscan代码，转载的，可供大家学习一下！-verilog code written keyscan, reproduced, and for them to learn about! Thanks
clock_generator
- clock generator verilog代码，供大家参考-clock generator verilog code for your reference
chap3
- 一些简单模型的verilog代码，对学习很有帮助-Some simple model of verilog code, very helpful for learning
chap5
- 一些简单模型的verilog代码，对学习很有帮助-Some simple model of verilog code, very helpful for learning
ADC0809VHDLcontrol
- 基于VHDL语言，实现对ADC0809简单控制。 -Based on the VHDL language, to achieve simple control of the ADC0809.
EDA
- EDA数字电子钟课程设计。时钟自动计时，并且将计时数据传送至显示管显示。-EDA digital electronic clock curriculum design. Clock automatic timing, and timing data will be sent to the display tube display.
7segmentLED
- 7段数码管显示源代码。基于VHDL语言，实现对7段数码管显示。-7 segment LED display source code. Based on the VHDL language, achieving seven segment LED display.
BCD
- 基于VHDL语言，实现二进制转换为BCD码。-Based on the VHDL language, to achieve a binary code is converted to BCD.
4LED
- 基于VHDL语言，实现对4位数码管显示。-Based on the VHDL language, to realize four digital tube display.
ethmac_latest
- 以太网MAC，已经通过测试，详细说明见内README-Ethernet MAC, has been tested in more detail, see README
6fifo
- 入门omnet++,omnet++仿真实验，欢迎大家一起交流。-It is very useful for student who study omnet++.