资源列表
sopc_builder_tutorial
- This application ready to run about use altera monitor program with de2 sample processor
ASY_FIFO
- 用Verilog编写的异步FIFO，可以方便的实现同步异步的转换，在全局异步局部异步的系统中得到广泛应用-ASY_FIFO written with verilog,and it is very useful in a GALS system
DDS_VHDL
- 基于FPGA环境的直接数字频率合成器的源代码-16 accumulator
VHDLdesign
- vhdl基础详解，有实例分析，适合初级eda学者学习-vhdl-based Xiang Jie, there is a case study, for academics to study the primary eda
clockVHDL
- 采用自顶向下设计方法，由秒计数模块、分计数模块、时计数模块、时间设置模块和译码模块五部分组成。-Using top-down design methodology, from the second counter module, sub-counting module, when the counting module, time setting module and decoding module of five parts.
chufaqi
- VHDL除法器设计，配合移位减法方式设计除法器以节省硬件成本-VHDL divider design
eetop.cn_digital_clock
- 基于VHDL的数字时钟设计课件，简单，实用-VHDL-based Digital Clock Design Courseware
JohnsonCounter
- 约翰逊计数器-Johnson Counter
RS_FPGA_papers
- 两篇RS编码fpga仿真的硕士论文，看完会对RS编码及其硬件实现步骤有清晰的理解。-2 RS codes fpga simulation master' s thesis, after reading the RS coding and hardware implementation will have a clear understanding of the steps.
RS_IPcore
- 一篇介绍变参数rs编码器ip核设计的文章。-Introduce a variable parameter rs encoder ip core design articles.
test_state
- VHDL code for UART transmission & reception.
VHDL_Golden_reference_EN
- 一本VHDL的知道入门书籍，英文的，比较实用！-To know a VHDL entry books, in English, and more practical!