资源列表
alu
- This arithmetic logic unit accepts 8-bit inputs, but it can easily be modded to higher bits. It supports the addition, subtraction, set if less than, AND, and OR operations. The operation to perform is determined by the 3-bit address bus.
ALTERA_JTAG
- Altera 的下载线官方资料，可以制作JTAG和AS模式的下载线-Altera download cable official information, you can create JTAG and AS modes download cable
fpga
- 学习FPGA很有价值的27个例子,以VHDL为例子，也可以用verilog-27examples of fpga for the leaner
CPLD
- 基于CPLD 的交通灯设计
frequency
- 在CPLD和FPGA上采用VHDL语言进行分频器设计，供设计者参考-digital frequency divider design with VHDL
Async-fifo
- Asynchronous Fifo tested and aproved.
VHDLexamples
- VHDL的27个设计实例 很实用的例子。对初学者有很大帮助-VHDL
System_Verilog_training
- montor的system verilog培训教程-system verilog training material from mentor
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
vprimer
- 硬件語言VERILOG介紹及範例. 適合初學者.-Verilog language Introduction and Examples.
Verilog-r2
- VLSI之硬體語言設計 --使用verilog 中文版.-VLSI hardware language design- Use Verilog.
HDL_design_stile
- HDL编码风格与编码指南. 包括: 1.命名规则 2.编码指导-HDL coding style and coding guidelines. Include: 1. Naming rules 2. Coding guide