资源列表
QPSK
- qpsk调制的vhdl程序 扩频 加扰 解扩 解扰-the qpsk vhdl program spread spectrum modulation scrambling despreading descrambling
horse_light
- verilog语言设计跑马灯程序 同步电路设计方式 经fpga验证-Verilog language design marquee program the synchronous circuit design fpga verification
uart
- verilog uart串口通讯程序设计 带个模块详细设计 及说明文档-Verilog the uart serial communication program design with the detailed design and documentation of a module
shizhongsheji
- 基于UP3borad开发板的时钟设计，可校时，设置闹钟等-Clock design based on UP3borad the development board, can the school, set the alarm
spartan3e
- this source is pin ucf for spartan 3e
carnegie-mellon-verilog
- verilog相关课程的讲义,讲解详细，对初学FPGA很有用的资料-verilog course handouts to explain the detailed and useful information for beginners FPGA.
Digital-baseband-system-
- 是基带方面的权威资料，好好参考会明白基带传输的原理和意义的-Digital baseband system modeling and design
nios
- 利用NIOS做的基于DE2的软核，包含锁相环，SDRAM等基本模块，可以运行基本程序-The soft-core NIOS to do based on the DE2, including PLL, SDRAM modules, you can run the basic program
FIBER_LOC_C
- CPU SYSTEM LOGIC CONTROL
wannianli3
- 一个用VHDL实现万年历的程序，用数码管显示-a calender based on VHDL,show numbers by Nixie tube
Count-display-circuit-design(VHDL)
- 用VHDL语言设计计数显示电路。设计输出为3位BCD码的计数显示电路。由三个模块构成：十进制计数器（BCD_CNT）、分时总线切换电路（SCAN）和七段显示译码器电路（DEC_LED）-VHDL language to count the display circuit. The design output for display circuit 3 BCD count. Consists of three modules: the decimal counter (BCD_CNT), time
shuokongfenpin
- 数控分频器。EDA实验设计。有详细的操作不瘦-It s important foe you!