资源列表
alucpu
- 计算机组成实验 西南交大 alu运算器 计算机组成实验 西南交大 alu运算器-Computer Composition experiment Southwest Jiaotong University the alu computing device
ML_506_3_lcd_1602
- lcd1602的四线控制的verilog源码，在ML506平台上已经通过验证-The lcd1602 four-line control of Verilog source code which has been verified on the ML506 platform.
bcdcounter
- 本系统能够精确计时，具有复位、计时功能，可显示计时时间的分、秒和0.1秒等度量，最长计时为10分钟。-a clock based on VHDL
I2C_VHDL_ISEProject
- I2C，总线设计，ISE完整工程，详尽设计，交流学习-I2C-bus design complete ISE project
apktools
- 该文件是用单片机，液晶显示器做的示波器课程设计。-This file is to do with the microcontroller, LCD display oscilloscope curriculum design.
fir1
- system generator 构造fir滤波器模型结构-system generator constructed fir filter model structure
cordic_cells3
- system generator环境构造cordic运算模块-cordic computing module of the system generator environment constructed
cic_5th_order_pipe1
- system generator 环境中构造cic滤波器模型-cic filter model constructed in the system generator environment
cic_decimator
- system generator 环境中构造cic数字滤波器 抽取-construct cic digital filter extraction system generator environment
qpsk_system
- system generator 环境中构造qpsk通信系统仿真-paparazzi the qpsk communication system simulation system. generator environment
AM2901
- 16为的AM2901的VHDL实现，是一个简单的vhdl实现代码-16-bits AM2901
verilog2
- Learning Verilog Chinese Version Part 2