资源列表
bcd7seg
- program vhdl bcd to 7segment altera de2
TP1_ALU
- Unité arithmetique et logique Nexys 2 board
usbblaster
- 老外原版的 altera usb 下载线 vhdl源码 -the altera usb download cable vhdl source
MOTO
- 步进电机的马达定位控制 vhdl 源码 内容包括 控制正反转，复位开关，设定的度数的二进制代码。-Motor stepper motor positioning control the vhdl source content control Reversible, reset switch, set the degree of binary code.
easyDerivator
- Easy derivator circuit, detects rising and falling edges of single signal.
lab5
- de2 altera 实验6 Adders, Subtractors, and Multipliers 答案-de2 altera experiment 5 Adders, Subtractors, and Multipliers answer
lab6
- de2 altera 实验7 finite state machines 答案-de2 altera experiment 7 finite state machines answer
clock
- 数字钟设计，完整的代码，适合初学者，完整的数字钟功能，verilog语言-verilog clock design ，fuction is really well .
electronic-organ
- 基于FPGA的电子琴，分为手动和自动模式，即按键发音，或通过蜂鸣器唱某一首歌（需自行设定音符），-Divided into manual and automatic mode, the pronunciation key FPGA-based keyboard, or sing a song (your own set of notes) buzzer
The-FPGA--fractional-divider
- The FPGA-based realization of the fractional divider
m_4_generater
- m序列发生器，verilog hdl语言 ，4位-m-sequence generator, verilog hdl language 4
the-use-of-ISE-explain
- ISE使用详解.ceb格式文件，让你知道如何使用ise环境- the use of ISE explain