资源列表
eight
- 八位同步寄存器（检测时钟上升沿，一个接受复位信号，八位输入赋给八位输出）-eight bit registered
mc
- 可控脉冲发生器:采用1KHz的工作时钟，初始化周期为2.5s，占空比为50 ，所以周期（T）初始化为2500，占空比（Result）初始化为1250；用按键S1、S2、S3、S4分别实现周期增大、周期减小、占空比增大、占空比减小。-Controllable pulse generator
ZXS6M
- ZXS6M的XILINX FPGA开发板的全套资料，包括用户手册、电路原理图、实验手册、实验代码等，该电路板功能非常全，实验涵盖了所有Spartan6芯片的常用功能，对想熟悉XILINX的新手来说是非常好的学习资料-The full set of data ZXS6M XILINX FPGA development board, including user manuals, circuit schematics, lab manual, test code, etc., the circuit
rank_exam
- 基于systemverilog的高考学生个人信息数据库，并带有排序功能-Based systemverilog entrance pupil personal information database, and with the sort function
uart_test
- 串口传输 verilog 实现
PS2
- ps2键盘连接口程序，通过键盘控制开发板的数码管显示字符。-ps2 keyboard connector program, display characters from the keyboard to control the development of the digital board.
key_smg
- FPGA 开发板按键消除抖动，可以修改程序使得按键抖动受控制。-FPGA development board to eliminate jitter button, you can modify the program so that the key jitter under control.
division
- 分频器,偶数分频 奇数分频 小数分频 不同方法实现不同种类分频 -Divider, even odd frequency divider fractional different ways to achieve different types of crossover
blif2vhdl-v1.1
- 将BLIF（Berkeley Logic Interchange Format）格式的电路转换为VHDL代码，使用perl编写，需要perl环境才能使用。 内含BLIF格式的官方说明。-Translate BLIF（Berkeley Logic Interchange Format）circuit to VHDL descr iption, the translator need perl environment to run. Please check you have related t
vending-machine
- 用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。-Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.
06_sled
- 用Verilog HDL语言编写数码管静态显示-Use Verilog HDL language digital tube static display
07_dled
- 用Verilog HDL语言编写数码管动态显示-Use Verilog HDL language dynamic digital tube display