资源列表
clock
- 一个能在电路板上实现时钟显示功能、计数功能、闹钟功能的VHDL源码-One can achieve on the circuit board clock display, counting function, alarm clock function VHDL source code
sdram_module3
- 能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写-can complete read or write sdram， only include Verilog code and no simulation files
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
17_usb_device
- Ch376控制器的控制程序，用于完成USB接口-Ch376_controller code by Verilog，used in USB communication
13_flash
- 用于读写8位数据口的FLASH芯片，使用Quartus II开发，Verilog文件-used to read or write the 8bit Flash Chip,developed by Quartus with Verilog language
23_lan
- Lan芯片ENC28J60的驱动程序，Quartus II开发，Verilog编写-the driver for a Lan Chip ENC28J60，developed by Quartus II using Verilog
1122334455
- 设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能-Design of a decimal counter, a display position with the count clock in eight digital tube rolling around functions
fpu_double_latest.tar
- 经过FPGA验证的VHDL全精度浮点运算单元-double floating point unit in VHDL
para2serial
- 并串转换模块，用于serdes编码器后面的部分，转换后用于LVDS发送。-And string conversion module, part of the back of the encoder for serdes, after conversion to LVDS transmitter.
74LS160jishuqi
- 74ls160十进制可预置计数器VHDL语言代码-74ls160 decimal VHDL language code can be preset counter
the-elimination-of-key-debounce
- 当按一次按健时，由于按健有反应时间、有抖动，可能你按一次机器感应到几次，防抖就是让在按键正常反应时间内机器只感应一次按键效果，防止误操作，本文是基于FPGA的按键防抖程序代码，用的是VHDL语言，内容包括原理，实际操作及源码等。-When you press a pressing health, because according to health have reaction time, jitter, you may press machine senses a few times, ima
the-examples-of-vhdl-program-
- 一共有100多个vhdl语言的编程实例，内容包括整个编写流程，可以帮助很好的掌握VHDL的要领，开拓思路，是练习学习该语言的很好的程序实例-Multiple instances of 100 vhdl programming language, including the entire preparation process, you can help a good grasp of the essentials of VHDL, explore new ideas.