资源列表
beep
- 蜂鸣器输出报警声实验 滴。。滴。。滴。。 -Buzzer output alarm sound experiment Drops. . Drops. . Drops. .
i2c_4163okok
- 利用Altera的Qsys生成片上系统SOC，利用CPU进行I2C的配置电路。-Use of Altera s Qsys generation system on chip SOC, the use of the CPU I2C configuration circuitry.
EDA
- 电子时钟 基于VHDL设计的建议电子时钟-DIGTAL CLOCK
switch_9
- 使用systemverilog语言写的4端*换机，你可以学习使用systemverilog-use systemverilog write 4 port switch,you can learing systemverilog language
uvm_switch_8
- 使用uvm验证环境搭建的testbench，主要验证switch的功能。可以学习uvm的简单功能-use uvm set up testbench ,the mainly focuse is verification swtich,you can learning uvm sample fucntion
XN703A_PRX
- 西南集成XN703A接收端移植代码，自己移植的，有些累赘代码没删-Southwest Integrated XN703A receiving end porting code, their transplant, did not delete some redundant code
p21
- mips pipeline的源代码，很简洁，很适合新手使用。大学三年级的必修课。-mips pipeline source code, very simple, very suitable for beginners to use. University of grade three compulsory.
DAC900
- 自己写的，FPGA为Cyclone ep1c12q240c8，dac芯片是DAC900。fpga内置ram存储波形数据，发送给dac900产生波形。用VerilogHDL编写。-Write your own, FPGA as Cyclone ep1c12q240c8, dac chip is DAC900. Built-ram fpga store waveform data, waveform generated is sent to dac900. Written VerilogHDL.
shumaguan-Verilog
- 简单的数码管电路设计实现代码 verilog-Simple digital circuit design implementation code verilog
IPRAM
- FPGA内置RAM,调用tools里面的IP核，生成一个双口的RAM，用来存储数据。然后可以用SignalTAP II查看波形或者数据。-FPGA built-in RAM, which is called IP core tools to generate a dual port RAM, used to store data. You can then view the waveform or use SignalTAP II data.
9288Test3
- AD9288 100MhzAD转换芯片的控制代码，用Verilog语言实现。采集数据存储于FPGA内置RAM中。-Conversion chip AD9288 100MhzAD control code, using Verilog language. FPGA collected data is stored in the built-in RAM.
uart_my
- vhdl语言实现UART的接收，发送，已成功应用-uart receiver and transmitter descr ipted in VHDL language,which has been used successfully.