资源列表
100vhdl4
- VHDL源代码100例（1）带有目录！请仔细查看！
jtd
- 主干道和支道红，绿，黄灯变化，并在数码光上显示出时间-Trunk Road and support Road, red, green, yellow change, and digital light show time for
ahb2apb
- Verilog实现的AHB2APB bridge代码-Verilog code to achieve the AHB2APB bridge
61EDA_C41
- 该文件写了关于verilog的lcd显示信息，是很有用的资源-The verilog file written on the lcd display information, useful resources
I2C
- I2C协议设计实现，采用Verilog HDL语言编写-I2C
test-of-reaction-time
- 利用DE2开发板设计一个，测试反应时间的程序，并把时间显示出来。-Use DE2 development board to design a test of reaction time program, and the time is displayed.
LED点阵
- 大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。-big screen led to the dot matrix display driver timing. The use of VHDL descr iption language. Rom which documents can be automatically generated using lpm_megcore.
sd_ctrl
- 利用verilog实现对SD卡的控制，可以实现对SD卡的读写。-Verilog SD
src
- 12秒定时控制电路: 当12秒定时时间结束时，L1指示灯熄灭，L2指示灯以每秒5次速度闪烁。-12 seconds timing control circuit: When the 12 seconds when the timer expires, the indicator goes off L1 L2 indicator flashes 5 times per second speed.
CK20-VHDL
- 经典ＣＫ２０时钟程序，实现了时钟的时，分，秒记数，并可以重调，置０-classic procedures CK20 clock and realized the clock, minute and second count, and can be re-emphasize that the Home 0
des_encoder
- 基于FPGA用verilogHDL设计的des加密模块，供FPGA学习者参考学习，本人设计-a code for des encoder by verilogHDL based on FPGA
09_uart2
- 串口字节收发通信，可以从PC机上通过串口调试助手输入一个字节然后从串口调试助手的接收区查找你输入的字节-Serial bytes to send and receive communication from the PC through the serial port debugging assistant enter a byte and then find your input bytes from a serial debugging assistant reception area