资源列表
dspbuilder
- ALTERA的dspbuilder教程，很详细-ALTERA DSP-BUILDER TO DEVELOP PROJECT
PCIdataout
- 包含数据发送到C程序与Verlog程序,包含数据发送到C程序与Verlog程序-C program containing the data to be sent and Verlog program
arbitrator
- arbitrator for network on chip
PS2
- FPGA外部PS2j键盘部分代码，FPGA芯片采用xilinx sptan3e 可以实现键盘与串口的通信-The FPGA external PS2j keyboard part of the code, the FPGA chip using xilinx sptan3e can realize the keyboard and a serial port communication
Rxd-new
- FPGA串口部分发送部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA与电脑的通信-FPGA serial sections to send code, the FPGA chip using xilinx sptan3e can implement on FPGA and computer communications
TXd_FIFO
- 用FPGA 串口通信发送部分代码，FPGA芯片采用xilinx sptan3e 可以实现FPGA向通过max232电脑发送数据-The FPGA to send part of the code, serial communication, the FPGA chip using xilinx sptan3e can implement on FPGA send through max232 computer data
key
- 实现FPGA 按键控制部分代码，FPGA芯片采用xilinx sptan3e 可以实现按下按键后FPGA通过max232给电脑发送数据-Achieve FPGA button control part of the code, the FPGA chip using xilinx sptan3e can realize after press the button the FPGA through max232 send data to a computer
serial-ports2
- verilog语言 12位串行数据传输转换为并行传输-12bit parallel to serial decoder and aynthesis result
second
- 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design,
RISC_SPM
- 可以完成简单指令集的八位ALU,指令集包括 NOP ADD AND NOT SUB RD WR BR BRZ-it s an 8 bit risc alu.
lab1_multicycle_dds
- 生成一个多周期直接信号数字合成器的Verilog代码，已在matlab中测试生成信号的频谱纯度符号要求-Generate more than one cycle of the signal direct digital synthesizer Verilog code, has been tested symbol require spectral purity of the signal generated in matlab
start_lab4
- 用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数- Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0