资源列表
tx_buffer_inband
- FPGA,TX发送模块VHDL程序。-tx buffer inband VHDL
Verilog135
- VERILOG实用小例，约135个，特别对于初学者很有用处-VERILOG Practical cases, about 135, particularly useful for beginners
simple_CPU_VHDL
- 简单的CPU的VHDL设计 vhdl代码和cpu设计过程--Simple CPU design of the VHDL code and VHDL design process cpu
Verilog-Code-Receiver
- Verilog Code for Receiver USART
Verilog-Code-Transmitter
- Verilog Code for Transmitter USART
38-always
- 此程序采用always语句实现3-8译码器功能，仿真波形正确。-This program uses the always statement to realize 3-8 decoder function, simulation waveform is right.
3-8-assign
- 此程序采用assign语句实现3-8译码器功能，仿真波形正确。-This program uses the assign statement to realize 3-8 decoder function, simulation waveform is right.
cordic16
- 16位cordic算法代码，可用于软件无线电理念下的数字接收机-the 16 bits cordic codes in VHDL
asyn_fifo
- verilog asyn_fifo,内含详细说明,同步FIFO为TPRAM-asyn_fifo include detailed instruction，Synchronous FIFO for TPRAM
TCAM
- 基于TCAM的高速路由查找，逻辑实现深度为32的内容查找，得到索引和命中指示-TCAM lookup based on a high-speed routing logic to realize the depth of content to find 32, get indexed and hit instructions
syn_fifo
- Verilog，syn_fifo ，内含详细说明，同步FIFO为TPRAM-Verilog, syn_fifo, containing detailed instructions for synchronous FIFO TPRAM
mux-demux-lab
- mux模块及demux模块实现，包括代码和相关讲解，可以参阅。-mux and demux model,including VHDL code and process