资源列表
EDA
- 通过MAXPLUS软件做时钟信号发生器，可通过外部的拨码开关进行清零和预置数-Software made by MAXPLUS clock signal generator is available through an external DIP switch and preset number of cleared
2-10
- verilog写的2进制转换10机制代码-source for 2~10 with verilog
fifo
- fifo使用手册，对于用IP core使用非常方便-fifo manual, for use with the IP core is very convenient
Code2
- 可以看一看，内容不多，几个源代码，就是这么多了。-Can take a look at the content more than a few source code, is so much more.
AVerilogHDLTestBenchPrimer
- VHDL的验证练习题，对于新手是很好的练习机会-VHDL validation exercises for the novice is a good practice opportunity
fir
- 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
electricdesign
- 用硬件电路实现简单音乐播放，基于Quartus平台。-The hardware circuit with simple music player, based on Quartus platform.
step
- 基于Quartus开发平台的3相6拍的步进电机-Quartus development platform based on the three-phase stepper motor 6 shooting. . . . . . . . . . . . .
CPU_1
- 此文件为cpu的verilog学习代码，从最简单的cpu开始学习-This file is cpu to study the verilog code, from the simplest cpu to start learning
AI-FSM
- 游戏AI 有限状态机的示例代码 FSM-FSM FSM FSM FSM FSM FSM FSM FSM
51_cpld_bus
- 实现51单片机与cpld的总线连接,经过调试，希望对大家由用-MCS51 and cpld interface using bus method