资源列表
and_2
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个与门。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware descr iption language to achieve an AND gate.
ram
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware descr iption language to achieve a RAM memory.
signal_output
- 本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
EDA
- VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda
shumaguan
- fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University
DDS
- 本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of t
PCi_Bridge
- Opencore的IP Core，有实际合成过，可以用，大家参考-Opencore of the IP Core, there is a practical synthesis that we could use, we refer to see
FPGATIMEING
- TIMING LEARNING -TIMING LEARNING
LC_txmit
- FPGA UART transmit and so on
VHDL-Handbook
- VHDL handbook is very nice and suitable guide to HVDL language
Verilog_Digital_Design_Synthesis
- Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996