资源列表
PROGRAMMING
- 怎么编程设计好CPLD，外文资料，对学CPLD/FPGA的人应该有帮助的-Programming how good CPLD, foreign language materials, learning CPLD/FPGA of the people should be helpful
Seven-Segment-Decoder
- 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
CPLDFPGA
- 怎么编程设计好CPLD，外文资料，对学CPLD/FPGA的人应该有帮助的-Programming how good CPLD, foreign language materials, learning CPLD/FPGA of the people should be helpful
CPLD
- 天祥视频中的所有程序，希望能对爱好CPLD编程的人有所帮助-Tienhsiang video in all programs, hoping to those who love CPLD programming help
clock
- 具有定时可调多功能数字电子钟，本人已经在fpga上调试成功-With adjustable multi-function digital electronic clock timer, I have been successful in the fpga debugging
flash_player-2008920201813708
- 实现wav解码，用VHDL编写，在quarters下运行，用于FPGA，CPLD稍作修改也可用-Wav decoder implementation using VHDL written to run in the quarters for the FPGA, CPLD some slight modifications can also be used
FPGA2SRAM
- 利用FPGA向SRAM中传输数据，可用于FPGA芯片的初始化和配置-The use of FPGA to transmit data to the SRAM, FPGA chips can be used for initialization and configuration
FIR
- FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
rs_5_3_gf256_latest.tar
- VHDL传资料的详细功能、包含内容说明(至少要20个字)。尽量不要让站长把时间都-VHDL
soc-OverviewProcessors.pdf
- 几款处理器相互比较，包括EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO(powerpc)-OVERVIEW-EXCALIBUR LEON MICROBLAZE NIOS OPENRISC VIRTEX II PRO(powerpc)
m_divider_int
- 14bit pipeline 除法器，在Xilinx V5上可以跑到100M，输出延时3cycles-14bit 100M pipeling divider
URAT_VHDL_CODE
- altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.