资源列表
TestBench
- TestBench for stop_watch in VHDL
division
- Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB-Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB
fibonacci
- it is a code to find fibonacci.
vit_dec_with_notes
- 带有注释的维特比译码器。经过试验完成，准确无误。-Annotated with Viterbi decoder. After test completion, accuracy.
NIOS2float
- NIOS II中计算浮点数乘除法的函数，可以极大地缩短浮点数运算的执行时间。-Floating-point multiplication and division of functions computed NIOS II, can greatly shorten the execution time of floating point operations.
seuVerilog
- 基于导频的ofem系统的信道估计和均衡Verilog建模-ceu Verilog
基于FPGA的自适应数字频率计
- 基于FPGA的自适应数字频率计，测量范围1Hz-99.9MHz,FPGA-based adaptive digital frequency meter, measuring range 1Hz-99.9MHz
VHDLSourceCodeFormax5236
- 一个max的vhdl源码 一个max的vhdl源码
counter
- 带异步复位功能的8位二进制加法计数器的行为描述-With asynchronous reset counter 8-bit binary adder descr iption of the behavior
vhdl
- VHDL 电子时钟程序！能实现简单的计时功能-VHDL clock
FPGA-convolutions-encoder
- 卷积码是数字通信中很重要的一种差错控制编码 具有很好的性能,用硬件的形式描述具有速度快，便于修改的优点，通过该种方法设，计的编码器经测试运行可靠正确。-Convolutional codes are very important in digital communication error control coding with a good performance, with the descr iption of the hardware in the form of a fast, eas
filter_512
- FIR低通滤波器 veilog源代码 参数自行调整可实现带通，低通，高通-FIR low pass filter