资源列表
一些译码器源代码
- 内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code
DECODE
- 利用状态机将并口发送的六组8位数据转换成串行正负脉冲数据发出。-Using the state machine will send the six groups of parallel data into serial 8-bit data to issue positive and negative pulses.
sw-led
- 用一个开关SW来控制一个灯的开与关，程序简单，可以用来熟悉开发过程。-SW with a switch to control the opening and off a light, simple procedures can be used to familiar with the development process.
SD_W_R
- SD卡读写源代码.用Verilog编写.很不错.值得借鉴.特别对SD卡开发的人员!
lcd_control_rtl_v3
- LCD display driver for xilinx fpga
OV7670_config
- 本代码主要实现OV7670的初始化配置，包括主模块及参数设置、I2C传输模块！-The main achievement of the initial configuration code OV7670, including the main module and parameter settings, I2C transmission module!
clock
- vhdl写的电子钟例程，包括多个文件，者的参考。内容简练。作为教学用的。
CPLD_Config
- 用Altera CPLD做为控制器从Flash上读取image文件对Altera FPGA编程-Altera CPLD used as a controller to read image from the Flash on the Altera FPGA programming
tlc5620_out_sin
- 用ＦＰＧＡ操纵ＴＬＣ５６２０DA转换器，用ＶＨＤＬ语言编写，调试通过，并输出正弦波。-Manipulation TLC5620DA converter with FPGA using VHDL language, debugging through, and the output sine wave.
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
altera_europa_support_lib
- FPGA 的高级运用原有代码，用于niosII的开发参考-NIOSII resources
C_ADDSUB_V1_0
- 针对xilinx器件的重要库文件，能够加快基于xilinx器件的工程开发，提高系统的性能。-For important library xilinx devices, to accelerate project development based on xilinx devices to improve system performance.