资源列表
rtl_DRAM
- 本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.-program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.
QuartusII_error_Analysis
- altera fpga编程过程中常出现一些错误及其消除方式，属于集体智慧的结晶-altera fpga programming mistakes often occur during its elimination method, belonging to the crystallization of collective wisdom
MIPS32
- 此資料夾為實現一單一時脈週期MIPS32處理器架構源碼，包含了控制單元、資料記憶體、資料路徑、指令記憶體四個部分，以程式碼: (共10個) instruction_mem.v、data_mem.v control.v、alu_control.v program_counter.v、reg_file.v alu_32bit.v、adder_32.v、sign_extend.v來實現。-MIPS (originally
i2c_master_top0004
- 基于VHDL的I2C程序0004,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0004, a very good paper and procedures, we quickly under ah
clock
- 这是一个用VHDL语言编写的数字电路程序，仅供学习参考。-This is a language with VHDL digital circuit procedures, only to learn the reference.
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
rsencoder.tar
- RS Encoder RTL verilog Code
SECLOCK
- 我从一本书上抄来的 但用MAX+PLUSII编译有些问题 初学者 见谅-from a book copied but with the MAX PLUSII compile some of the problems beginners forgiven
VERILOGchaffic
- 用VERILOG 语言编写的十字路*通灯程序-TRAFFIC LIGHT
control_pipeline.zip
- Verilog components for a pipelined cpu simulation,Verilog components for a pipelined cpu simulation
i2c
- I2c serial bus protocol
rsencoder_latest.tar
- reed solomon encoder in verilog-reed solomon encoder in verilog