资源列表
Verilog_Coding_for_Logic_Synthesis
- 可综合的Verilog编码，很不错，学习Verilog必看。不容错过-Can be integrated Verilog coding, very good, a must-see learning Verilog. Not to be missed
datacompare
- 采用verilog语言来进行数据比较器 附带仿真波形-Verilog language used to compare data with simulation waveform control
USB_HID
- 全名的USB HID协议例子.包括HIDtoUARTExample MouseExample等例子-Full name of the USB HID protocol examples, including examples such HIDtoUARTExample MouseExample
MYPCI
- PCI VHDL程序，根据PCI通信协议编写的，，，没有用IP核，。。。本人接触PCI不久，次代码可能会存在些问题，请各位高手指点指点，小弟不尽感激-PCI VHDL procedures, according to the PCI communication protocols written, without using IP cores. . . I contact PCI soon, there may be some minor code issues, please master g
clock
- vhdl 电子钟 计时 上下午 整点报时-VHDL Electronics afternoon bell time on the whole point timekeeping
VHDL语言实现的arm内核
- 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，
IIC
- 编写FPGA 的模拟I2C通信，用的是altera验证(The preparation of FPGA analog I2C communication, using Altera authentication)
Verilog_USB_OUT
- USB out，使用Verilog写的，包含完整工程、文档和USB芯片的固件-USB OUT, VERILOG, Including project、document，USB firmware
dds
- 齿轮系统噪声预估及声诊断方法Noise Prediction and sound gear system diagnosis-Noise Prediction and sound gear system diagnosis
E7_2_IntBitSync
- 位同步的VHDL实现，代码可综合。很好用！(Bit synchronization of the VHDL implementation, the code can be integrated. very useful!)
mul
- VHDL实现通用乘法器，位数可以自定义，通过移位相加实现-VHDL generic multiplier, the median can customize the sum achieved by shifting
64bitALU
- 64 bit alu structure vhdl code -64 bit alu structure vhdl code