资源列表
MATHM60
- 用Verilog语言写程序，实现对初始计数器60进一-Verilog language used to write programs to achieve the initial counter 60 a
yuruyen
- 0..7 to Led counters 2009
ldpc_encoder_802_3an
- ldpc_encoder for 802.3an
Example-b3-1
- 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the sof
DDS
- VHDL高级语言利用DDS实现信号发生器的功能，频率波形可调-VHDL DDS
vhdl交通灯
- 实现十字路口两个交通灯的功能，完整实验报告，含源代码(The realization of the intersection of two traffic lights function, complete experimental report, including source code)
ex3_4_rs232
- 基于FPGA的串口通信程序，简单实用，很好-FPGA-based serial communication program, simple and practical, very good
signal_output
- 本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
VHDL硬件描述语言教学
- VHDL硬件描述语言教学 VHDL硬件描述语言教学-VHDL hardware descr iption language teaching and VHDL hardware descr iption language teaching and VHDL hardware descr iption language teaching
S16_ADC
- 基于xilinx的vhdl采集程序，芯片为AD7923-Based on the xilinx vhdl collection procedures chip AD7923
niosii-triple-speed-ethernet-4sgx230-qsys-131
- Altera公司出的三速以太网例程，工程编译完了可以用niosii直接生成simple_socket_server，希望有用。(Altera company out of the three speed Ethernet routines, engineering finished, you can directly generate simple_socket_server using NiosII, I hope useful.)
74HC194
- 74ls194 基于verilog语言的实现 -Verilog language 74ls194 based on the realization of