资源列表
Ethernet_Accel_Design
- altera官方以太网例程（基于niosII）-Accelerating Nios II Ethernet Applications User Guide
LED
- QuartusII 9下的LED灯示例，很简单的例子，可以直接运行-The sample of LED of quartus II 9.0 with the language of Verilog
Simple_Logic_Continue
- quartusII 9编写的74161模块，简单的例子，可以直接运行-The module 74161 with the language of verilog
XC2C
- 基于FPGA的8路心电数据采集，发送给MSP430.-FPGA-based 8-channel ECG data acquisition, send MSP430.
fenpin
- 关于FPGA的分频程序，使用VHDL书写，可用于模块化编程-fractional frequency
shuzishizhong
- FPGA代码，数字时钟，可调小时，分钟，秒钟，调节时闪烁-digital clock
seg
- 四位一体数码管显示，实现数码管动态显示。已经测试，很好用！-Four digital tube display, realize the dynamic display of digital tube.Already test, very good!
i2s_latest
- Details Name: i2s Created: Mar 22, 2004 Updated: Jan 10, 2014 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Communication controller Language: VHDL De
my_uart2
- 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Sum
vga256
- 这是一个Verilog的VGA程序，可以再显示屏上显示8种颜色-This is a VGA-Verilog procedures can be shown on the display 8 colors
PCIIP-core
- 基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v” Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and write address generation and full, almost full, empty and almost empty status generatio
sp605_pcie_13.2
- 基于FPGA，pcie开发的源码程序，已经经过测试，上传来给其他爱好者学习交流。- input user_clk, input user_reset, input user_lnk_up, // Tx input [5:0] tx_buf_av, input tx_cfg_req, output tx_cfg_gnt,