资源列表
doc
- VHDL：用状态机的方法实现一个8位乘法器-VHDL: state machine method used to achieve an 8-bit multiplier
vhdl_zhiliudianjikongzhiqi
- 用vhdl编写的一个直流电机控制器-Vhdl prepared using a DC motor controller
compare
- 简单的原理性ROM 存储了地址的反码 可以用LED显示-Simple principle of ROM code memory of the address counter with LED display can be
c16_multiple
- 精通verilog HDL语言编程源码之2--常用乘法器设计-Proficient in verilog HDL source language programming of 2- Common Multiplier
FIFO
- 异步FIFO设计 FPGA代码 Asynchronous fifo-Asynchronous fifo
8 bit, bit by bit procesing unit
- This module does an bit by bit sum, 2 complement,or,and,xor,and not operation of two 8 bit numbers (not and 2 compliment its just 1 number) It has two shift registers that feed your numbers to the procesing unit with an external load/shift signal and
加法
- 测试向量波形产生：VHDL实例---加法器源程序 -test vector Waveform Generator : VHDL example -- Adder source
array_multiplier
- verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y -verilog codearray_multiplieroutput [7:0] product input [3:0] wire_x input [3:0] wire_y
2bit_ALU
- This is a source code of 2 bit ALU and this is in VHDL form.-This is a source code of 2 bit ALU and this is in VHDL form.
pwm
- 使用Altera公司的FPGA的软化，利用NIOS完成PWM功能-Using Altera' s FPGA softening, use NIOS complete PWM function
uart_async
- RS232串口通信代码，采用verilog HDL实现，在quartus上仿真通过并下载到fpga平台功能验证-RS232 CODE
PWM-generation-using-microcontroller
- PWM pulse generation using PIC16F877A