资源列表
divide
- 除法器-Divider
PWM
- Core_PWM,verilog语言编写，可用于电机驱动
LED
- LED跑马灯 代码为Verilog。已经在V5 ML506上验证过。 -LED Marquee code for Verilog. On the V5 ML506 has been verified.
zhegnxianbo
- 首先把正弦信号的数据写入存储器，通过控制程序给出的地址访问ROM存储器，不同的地址给出不同的数据从而将正弦信号读出来-First turn on the sine signal data writing memory, through the control program of the address given access ROM memory, different address given different data and the sine signal read out
9_timer
- fpga的nios timer程序，可快速了解fpga nios核的配置方法-fpga' s nios timer program, you can quickly learn how to configure fpga nios nucleus
07_rs232_echo
- Controller RS232 in VHDL
filtref
- fir vhdl programme altera
New-Text-Document
- AWGN verilog download form somewhsre in internet
DE1_pin_assignments_TFT_NEC6446
- de1 assignments for nec6446 tft vga display
ALU_verilog
- 用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件
serial_1
- RS232 protocol written in verilog There s four parts : top_level frequency receive data transmit data
time
- 电子钟实现 包含数字跑表 万年历 设置三个闹钟 时间，日期调整-Clock to achieve with digital stopwatch calendar set three alarm time, date, adjust