资源列表
lcd
- SPARTAN 3E 开发板驱动程序 Verilog源码 对于数字电路设计是很好的参考资料-SPARTAN 3E development board driver for digital circuit design, Verilog source code is a good reference
szshizhong
- VHDL语言实现数字时钟，并可以显示时和秒-VHDL, digital clock, and can be displayed and the second
4NandFlash.rar
- 基于verilog hdl 的Nand Flash控制代码,Verilog hdl-based control code of the Nand Flash
lcd
- It is a example about LCD by VHDL code
Multiple
- 高效的乘法器设计，既节约面积，又提高性能，同时减少开发周期-Efficient multiplier design, both to save space and improve performance while reducing the development cycle
fenpinqi-VerilogHDL
- 各种分频器的VerilogHDL语言编写，有通过计数器实现的奇分频，偶分频，任意分频-Various divider VerilogHDL language, there is achieved through the odd frequency counter, even frequency, any frequency
Lab-7(lcd-display)
- lcd display for spartna 3e..will display name sumam david...our hod name-lcd display for spartna 3e..will display name sumam david...our hod name....
dianti4
- 4层电梯，有各楼层的状态的详细解释 备注 状态分析-4 elevators, each floor has a detailed explanation of the status of state analysis Remarks
12864
- 12864说明 写明如何将显示器显示在相应的图片 完成显示功能-12864 instructions specify how to display images in the corresponding complete display
audio_io
- 关于cub1400的verilog驱动代码 已经通过测试-it s about ucb1400 code
CorePWM_RTL_Verilog
- Verilog_HDL源码 -Verilog_HDL source Verilog_HD L FOSS Verilog_HDL FO
EZ_USB_LOOPBACK
- 本程序：EZ-USB在slave fifo模式下，利用FPGA控制EZ-USB的数据读写-This program: EZ-USB in slave fifo mode, use the EZ-USB FPGA control data read and write