资源列表
encoder_state_v4
- motor phase count with A, B, Z phase
RS-232
- RS-232发送接受模块，测试好用，满足一般要求-RS-232 transmit and receive modules, easy to use test, meet the general requirements
lcd_test_pongball_crosshair
- lcd test_pongball crosshair model
rx_tx_demo
- 用verilog实现的少量字符串的连续收发，添加了FIFO模块，稍微修改下就可以使用。-Receive a small amount of a continuous string of verilog implementation, added FIFO module, can be used under slightly modified.
SMBus
- SMbus通讯协议的Verilog程序段，已通过Moldesim的仿真，可用-Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available
temperature
- 基于VHDL控制的DS18B20温度测量程序，精确到小数点后两位，在实验板上通过；
dianti.rar
- 以FPGA技术为基础，以VHDL为语言，以QuartusII为工具，设计一个5层楼的电梯控制器,To FPGA technology, to VHDL language to QuartusII as a tool to design a 5-story elevator controller
i2c_master_byte_ctrl
- I2C控制，I2c master-bitctrl。v控制信号-I2C CONTROL
IIC
- 使用verilog HDL编写IIC代码，通过FPGA读取mpu6050数据，其他IIC器件代码类似-IIC written using verilog HDL code, read mpu6050 data through FPGA, similar to other IIC device code
filter
- program d un filtre passe bas ordre 30
alu_ocle
- Unidad Aritmético Lógica
i2c_slav_tb4
- verilog, i2c slave, 两个输入端口，可自由切换。-verilog, i2c slave, two input ports are free to switch.