资源列表
pwm_sti
- This code has SPWM generation with 8 bit feedback.with the help of feedback can adjust the amplitude of sine wave.
led_blinking
- This code is for led blinking in vhdl for fpga compiled in altera Quartus 13.
pwn-FOR-60-HZ
- THis code is for Spwm based inverter.with 25khz carrier frequency of pwm and 60 hz frequency which is modulated on pwm.compiled in altera Quartus
CRC16
- CRC循环冗余校验码的执行与描述，以及实现CRC计算-CRC cyclic redundancy check code execution and descr iption
Verilog_32bit_Adder
- 32位超前进位加法器的改进Verilog实现-Improved Verilog implementation of 32 bit ahead carry adder
FPGA_NIOSII_USB
- FPGA_NIOSII的U盘存储，能够对U盘进行读写，文件为一个项目-FPGA_NIOSII U-disk storage, U disk can read and write files to a project
21
- 基于DE1的4位全加器（可视化），通过数码管显示，开关输入实现。-4 bit full adder based on DE1
tx__fsm
- 这是一个描述FSM的代码，是我project项目的一部分希望共享给大家，也和大家共同进步-This is a descr iption of FSM code is part of my project project hope for everyone to share, too, and common progress
VGAS
- vga for fpga vhdl so enjoy learn about vhdl
sycclk
- it s modul of clock in fpga vhdl where the cycle is 25 MHz enjoy
3180-bully
- the ball in fpga fixe or move it s the same enjoy it it
Display
- CPLD按键消抖控制,数码管显示。已调试通过。可直接使用-CPLD key consumer shake control, digital tube display. Debug through. Can be used directly