资源列表
sdram_led1
- 用于焊接硬件ＳＤＲＡＭ时调试，FPGA驱动SDRAM看能否工作，led可选用户自定义引脚-Used in the welding of the hardware SDRAM, FPGA driver SDRAM to see whether the work, led optional user defined pin
TXcontrol
- 在一个具有编解码，调制解调等的简单通信系统的硬件仿真中，发送端的时隙控制的VHHL源码-In emulation of a codec, modem, etc. have a simple communication system, the sender of the control slot VHHL source
div
- 10进制分频器,可通过简单修改代码实现任意进制的分频，简单有效-decimal divider
EORGate
- 鉴相器，用异或门实现的简单鉴相器，相同则输出0，不同则输出1-phase discriminator
seven-segment-encoder
- 七段译码器，实现七段译码器的显示功能，使用VHDL语言写成-seven-segment encoder
count_nixie
- 计数器加数码管译码，计数功能然后在数码管上显示，使用VHDL写成-counter encoder
fsmc
- fpga的fsmc通讯代码-fpga s fsmc communication codes
Proj_Cache
- 高速缓存的Verilog HDL实现。（包括直接相联和组相联）-Cache Verilog HDL implementation. (Including directly linked and set associative)
RS485
- verilog开发FPGA，实现RS485串口通信-RS485 driver for FPGA
SegLed_DynamCNT
- FPGA控制数码管动态显示,verilog编写-segled display dynamicly controled by FPGA
DC_MOTO_V1_0
- FPGA直流步进电机驱动程序，verilog编写-driver for DC moto controled by FPGA
STEP_MOTO_V1(3C10)
- 3c10 步进电机 FPGA驱动程序 verilog编写-3c10 step move moto controled by FPGA program write by verilog