资源列表
half_clk
- 用Verilog HDL语言实现的二分频，输出频率是输入频率的一半。-Using Verilog HDL language of the two frequency, output frequency is half the input frequency.
fpga_counter_Verilog
- 此文件是基于xilinx ise平台上开发的计数器，产生可调的脉冲，也可进行分频。-This document is based on xilinx ise platform counter, adjustable pulse generation, but also for the division.
fpga_sw_led
- 本文件使用FPGA模拟拨码开关，当拨码开关置0或1时，led灯也对应点亮-This file uses the FPGA analog DIP switches, when the DIP switch is set to 0 or 1, led lights lit correspondence
zadanie-1
- Project whitch implement picoblaze MCU and uart communication.
embedded-system-UTS
- this about embedded system-this is about embedded system
Reversible-Data-Hiding
- REVESIBLE DATA HIDING
hdb3_v3
- Quartus环境下使用Verilog编写的串口程序，RTL和时序仿真已过-Quartus under the environment of a serial procedures written in Verilog, RTL and timing simulation has be passed
uart_v1.1
- Quartus下开发Verilog编写的串口程序，主要包含串并互转模块等，通过RTL和时序仿真-Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed
HDLC
- Quartus下的HDLC编解码的开发，包含说明文档和设计报告，通过RTL和时序仿真-Quartus HDLC codec under development include design documentation and reports, by RTL and timing simulation
entity-fp-is
- 简易计算器4*4矩阵键盘输入,多个数值vhdl代码-Simple calculator 4* 4 matrix keyboard input, multiple values vhdl codes
eda
- 一百进制计数器，以十进制计数器为模板增加十位计数，可类比写出多位计数器。九十九清零。-One hundred binary counter, decimal counter increased ten count as a template, you can write a number of analog counter. Ninety-nine cleared.
429send
- 实现EP3C5E144型FPGA发送429信号，通过429板卡接收验证-EP3C5E144 type FPGA to send 429 signal, through the 429 board received verification