资源列表
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
scope-firmware
- Open-source Spartan-6 compatible project that implements a USB digital scope firmware by alown, including tests.
debouncer_vhdl
- RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
wu4g
- Wake up network layer for a Hardware based radio project, written in VHDL.
USRP-PID-Controller-clean
- PID feedback controller project for USRP1 boards (FPGA with a convenient analog front manufactured by ettus research). Implements a bitstream as well as python-based user interface.
tmds_decoder
- Tryout HDMI decoder for Xilinx-based boards, using SERDES logic. Different implementations.
s6iserdes-master
- ISERDES implementation and example code for Xilinx-based boards, e.g. Spartan 6.
FangDou
- 用Verilog语言编写的机械按键防抖程序，使用ISE10.0版本。-Verilog language used mechanical buttons stabilization program, use ISE10.0 version.
FangDou_reg
- 使用Verilog语言编写的机械按键防抖程序，采用移位寄存器的方法进行消抖。-Verilog language using mechanical keys stabilization program, the method of using a shift register eliminate shaking.
mileage
- 我用的是FPGA实现的，用来计算路程的，可以用在出租车的打表器，实现对里程的计数。-I use the FPGA to achieve。 It is used to calculate the distance, can be used in the taxi meter, to achieve the mileage of the count。
time
- 我用的是FPGA实现的，用来计算时间的，可以用在出租车的打表器，实现对时间的计数。-I use the FPGA to achieve, for the calculation of time, can be used in a taxi meter, to achieve the time count.
Divider_Verilog_ISE
- 用Verilog语言编写的分频程序，包含奇数分频、偶数分频等许多例程。-Using Verilog language division procedures, including odd division, even dividing and many other routines.