资源列表
ethcomm
- 转：FPGA Ethernet Communications Interface.-FPGA Ethernet Communications Interface
state_machine
- 适合初学者。简单的状态机，有8个状态,数码管输出当前状态的编号.基于Mars-XC3S400-F实验板-Suitable for beginners.A simple state machine, there are eight state, digital tube output the serial number of the current state. Based on Mars- XC3S400-f experiment board
seg70
- 适合fpga，verilog初学者。按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。以动态扫描方式在8位数码管“同时”显示0 7-According to certain frequency in turn to various digital tube COM client sends out the low level, at the same time to send out the corresponding data to the paragraphs.In
test
- Test Pattern files used for testing on embedded development board
CRC
- 能够实现S模式询问应答过程中的AP域编码模块，该模块完全按照260B协议编码-Mode S transponder can be achieved in the process of inquiry AP domain encoding module, which is fully in accordance with the 260B protocol encoding
Pre-Emphasis
- A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pree
VLSI4
- The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we report the consequences
1
- than dc parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64-Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carr
2
- for the first time, the impact of hotcarrier-induced gate capacitance variation on dynamic circuits in a VLSI chip. To investigate the mismatch drift due to the hot-carrier-induced gate capacitance variation, internal probing was performed at
4bit counter
- 4-bit synchronous counter counts sequentially on every clock pulse the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 )
sdram
- FPGA读写SDRAM。里面有详细的注释，供初学者参考，Verilog 语言-FPGA read SDRAM. There are detailed notes, reference for beginners,
DDS
- FPGA实现三通道DDS信号源Verliog程序-FPGA to achieve three-channel DDS signal source Verilog program