资源列表
cf-fft
- 用ip核实现fft。用vhdl编写。altera的fpga-Ip core implementation using fft. Written in vhdl
PPRAM-test
- 乒乓缓存，用vhdl编写，用fpga内部ram-Ping-pong buffer, using vhdl to write,
jtdverilog
- 交通灯，verilog，VHDL，modelsim-Traffic lights, verilog, VHDL, modelsim ,,,,,,,,,,
project_1
- 显示器显示有信号，能够看到分辨率信息为1280 x 720 @ 60P，显示器显示标准8 色垂直彩条-Display a signal, the resolution information can be seen as 1280 x 720 @ 60P, the display shows the standard 8-color vertical color bar
project_11_first_d1_HDMI
- 本代码将TW2867第一通道输出解复用以后进行BT.656格式的解析，然后将奇偶场合并为一帧存入DDR2，读取的时候使用双线性插值算法，将原始的720 x576的分辨率放大到800x600，然后在HDMI口输出。-This code will TW2867 first channel output demultiplexing after parsing BT.656 format, then the parity occasions and as a frame stored in DDR2,
MATLAB-and-FPGA
- 以Xilinx公司的FPGA为开发平台，采用MATLAB及VHDL语言为开发工具，详细阐述数字通信同步技术的FPGA实现原理、结构、方法以及仿真测试过程-In Xilinx s FPGA development platform, using MATLAB and VHDL language development tools, elaborated synchronous digital communications technology FPGA implementation princip
receive_uart
- fpga串口通信，接收模块程序.verilog语言编写-fpga serial communication, receiving module program
ps2
- 用verilog编写的PS/2通讯协议是一种双向同步串行通讯协议。-Verilog prepared with PS/2 protocol is a bidirectional synchronous serial communication protocol.
ad7266
- 实现FPGA对AD7266的控制，采用Verilog语言编写-FPGA to achieve AD7266 control, using Verilog language
kn_cnt16.v
- 可逆的异步计数器-Reversible asynchronous counter! ! ! ! ! ! ! ! ! ! ! ! !
the_last
- VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。-Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until
HDMI_ADV7511
- HDMI芯片ADV7511资料介绍，其中AN1270里面有一套DEMO源码，可以显示。-The information on the chip ADV7511 HDMI, which AN1270 document DEMO inside source confirmed with the DEMO display.