资源列表
FIFO
- Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit-Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit
KinetisIAR
- OSPF协议将网络划分为多个自治域进行管理，路由器根据在自治系统中的角色划分(IAR,ABR,BBR,ASBR)，除IAR外，一个运行OSPF协议的接口状态根据接口的不同类型可划分为 DR: Designated Router BDR: Border Designated Router DROther: Non (DR or BDR)-The OSPF protocol divides the network into several autonomous doma
16x2_lcd_display_driver_latest.tar
- verilog编写的LCD控制器，可以作为LCD的开发-verilog prepared by the LCD controller，It can be used as the development of LCD
my_sd_vga_test
- my_sd_vga_test,SD图像文件存储-my_sd_vga_test, SD image file storage
04_div_clk_1Hz
- verilog HDL 描述分频电路 产生1Hz脉冲方波信号 系统时钟频率50MHz-this is a divide circuit module to get a plus signal of 1Hz
08_counter_white
- verilog HDL 计数器 8位 计数值送数码管显示-this is a verilog file for counter
02_buzzer
- verilog HDL 驱动蜂鸣器 驱动频率可调 驱动频率在1KHz时 无源蜂鸣器声音较大-this is a verilog file to driver the buzzer
02_nonblocking_assignment
- verilog HDL file 非阻塞赋值描述 带仿真 用于理解 阻塞赋值与非阻塞赋值的区别-this is a verilog HDL file for non blocking assignment.
zhuangtaiji
- verilog一个有趣的状态机事例，简单易懂。适用于初学者。是一个小游戏的，sparten板子可用。 内含测试。-Verilog an interesting state machine case, simple and easy to understand. Suitable for beginners. Is a small game, sparten board available. Inclusion test.
test_rtls
- RTl hardware generation
usb
- usb2.0 vhdl 控制源码 资料可信 完全自编写。-usb2.0 vhdl
FPGA__source-code__Verilog
- FPGA部分基础功能源代码，适合初学者进行学习仿真，代码可读性强，通俗易懂，逻辑清晰。包括触发器，全加器，分频，并串转换，计数器，序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ