资源列表
gpr
- 32个寄存器组成的寄存器堆 用于在cpu设计中存储数据-made up of 32 regs be used to design single cpu
Alu
- alu cpu中的运算模块 可以进行加减等方面的运算-alu a part of cpu can add sub and so on
counter
- 计数器 用来计数 带有复位功能 用verilog语言编写-counter use for countering number use Verilog accelmber
lcd1602_test
- FPGA 实验：在液晶1602第一行显示Welcome to FPGA，第二行显示0-9的数字循环，并设置有复位键。学会了1602液晶每行显示的设计，理解1602液晶的具体结构，此程序基于Quartus的编程环境，采用Veilog语言编写。-FPGA experiment: the first line of LCD second show to FPGA Welcome, the 1602 line shows the digital cycle of 0-9, and set the res
AD0804
- FPGA之ADC0804实验（1）程序是用ADC0804显示00-ff（2）将其转换成0-255；（3）将其转换成0-5.0V； （4）如果输入电压大于2.5V，设定报警灯亮。此程序基于Quartus的编程环境，采用Veilog语言编写。-ADC0804 FPGA experiment (1) program is to use ADC0804 00-FF (2) will be converted into 0-255 (3) will be converted into 0-5.0V (
DA_TLC5620
- FPGA之TLC5620：将所给程序下载到实验箱，观察现象并结合现象理解程序的含义，使其实现单通道的DA转换：在按下通道的按键之后，用数码管显示输入的数字量，停止按键，数码管计数停止，继续按键则继续计数，按下复位键，则系统清零，数码管显示零值。此程序基于Quartus的编程环境，采用Veilog语言编写。-FPGA tlc5620: to the program downloaded to the box observed phenomenon and combined with the phe
Parallel_SQRT
- 32-bit parallel integer square root
VHDL-projects
- I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
fpga
- FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择 -FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade puls
lvds
- lvds通信协议程序，已调通,并包含一些相关资料-lvds communication protocol procedures have been transferred through, and contains some relevant information
5_ADC_Lab
- 基于altera公司MAX10型FPGA的ADC调试程序-ADC-based debugger altera company MAX 10 type of FPGA
6_USB_to_SDHC_Lab
- 基于altera公司MAX10型FPGA的usb至sdhc通信的调试程序-Altera company based debugger MAX 10 type of FPGA to sdhc usb communication