资源列表
testt2
- 由单片机和CPLD共同构成7位数字频率计-By the MCU and CPLD together seven digital frequency meter
test1
- 4位数字频率计的verilog HDL设计，精度比较准的-4-digit Cymometer verilog HDL design, the accuracy of the quasi-comparison
hex2rom_0241_Win32
- This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, Cyclone III edition (NEEK).-This SPI-mode SD Card controller is a
jc2_vhd
- jhonson counter using shifter
freqm
- frequency multiplier
flash
- flashing led example code
PCI_VHDL
- pci控制器的vhdl代码-pci vhdl
ide_control
- 三段式Verilog的IDE程序，但只有DMA部分，需要自己添加PIO的代码-Verilog three-step procedure of the IDE, but only parts of DMA, PIO required to add their own code
xapp851
- The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \rtl - HDL design files \sim - simulation files \synth - Synthesis related files \par - Place/Route related files-The xapp
Quartus_Clock
- 利用Quartus模块化层次化设计数字钟-Using Quartus hierarchical modular design digital clock
EP1C6_12_1_2_MOTO
- 基于ALTERA的cyclone 系列的控制电机的实验例程-ALTERA series based on the cyclone motor control routine of the experiment
SingleclocksynchronousdesignmetricCNTR
- 用VHDL 设计的单时钟同步十进制可逆计数器的设计-VHDL design using a single clock synchronization decimal CNTR Design