资源列表
ethmac10g_latest.tar
- ethmac10g_latest.tar.gz源代码-ethmac10g_latest.tar.gz source code
ac97_ctrl_latest.tar
- ac97_ctrl_latest.tar.gz源代码-ac97_ctrl_latest.tar.gz source code
wb_dma_latest.tar
- wb_dma_latest.tar.gz,请需要的下载-wb_dma_latest.tar.gz
hdb3
- vhdl语言实现的hdb3编解码的功能，已完成调试。-vhdl
VHDL_USERGUIDE
- 本书的主要的服务对象是熟悉硬件系统，而对软件的设计经验缺乏的工程师；叙述了VHDL的用法-This guide is intended for the engineer who is familiar with the principles of hardware design, but has little experience in designing with a language-based synthesis system. It describes the general c
base_fir
- 使用verilog 写的FIR滤波器，里面并有matlab程序，是从altera官网下来的。。希望对大家游泳。-Use verilog to write the FIR filter, which have matlab and procedures, are down from the official website of the altera. . Everyone would like to swim.
autoseller
- 自动售饮料机。用vhdl变写的自动售物品的程序。-Beverage vending machine. Writing vhdl variable with automatic procedures for the sale of goods.
lbuff_mem
- 延时代码,可以用在ＦＰＧＡ数据流水处理，图象处理，滤波-delay code
check
- 用Verilog实现的序列检测器，可以检测出任意规定序列-Verilog implementation using the sequence detector
I2C_SLAVE
- I2C_SLAVER FPGA 源码 已经验证-I2C_SLAVER FPGA
LVDS_DDR_List_FPGA2
- FPGA芯片与ADI公司的AD9779之间的通信，总共有四个通道，68对LVDS,采样时钟是122.88MHz-FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
sum_ten
- 十位累加器,EDA,FPGA,DDS信号发生器的相位累加器,可用.-Accumulator 10, EDA, FPGA, DDS signal generator of the phase accumulator can be used.