资源列表
单片机超声波测距程序
- 51单片机超声波测距程序资料,包括全部的原理图设计，实物图设计，还有完整的程序(51 singlechip ultrasonic ranging program data, including all the schematic design, physical design, and complete program.)
S3E_Ethernet
- acces to send the data on the internet
Project_III
- 16bit的ALU，完成加减乘数移位功能，使用verilog编写-16bit the ALU, multiplier displacement function to complete the addition and subtraction, using verilog write
fxy20114568_cdkzq
- 彩灯控制 fpga 数字电路设计-Lights control
uart
- VHDL编写的UART异步串行通信接口程序，，，经过仿真验证，简单易懂-VHDL prepared UART asynchronous serial communication interface program, through simulation, simple,,,,,
Xilinx_PCI_Express_IP_project
- Xilinx公司PCI Express IP核应用参考设计
FDK
- LCD1602控制VHDL代码，带有ADC和DAC采样，以及原理图和PCB版图供参考-LCD1602 control VHDL code, with ADC and DAC sampling, as well as schematic and PCB layout for reference
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help
(15-7-2)BCH
- Verilog HDL 语言编写的（15，7,2）BCH编码和译码功能-Verilog HDL language (15,7,2) BCH encoding and decoding functions
Clocking-resources-Spartan-6
- CLOCK RESOURCES FOR SPARTAN 6 LX150T.
TINY3
- verilog 编写的tiny cpu 代码，可实现简单的指令和计算-Verilog prepared tiny cpu code, can be simple instructions and the calculation
shuzitongxinxitongjianmo04
- 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第四部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the fourth part of the digital communication syst