资源列表
Verilog-DRAM
- fpga(veriloh hdl)编写的SDRAM程序说明 -fpga(veriloh hdl)SDRAM
HDLcodingstyle
- verilog HDL 代码综合风格，非常适合初学者-verilog HDL code integrated style, very suitable for beginners
xapp592
- sdi的发送和接收程序，使用XILINX ip核实现-SDI sending and receiving procedures, the use of XILINX nuclear IP
Oscilloscope
- 开发板上芯片是cycloneII，利用Verilog HDL语言编写程序，将波形和波形数据显示在2.4寸TFT液晶屏上。在开发板上成功实现。-Development board chip is cycloneII, use of Verilog HDL language programming, the waveform and waveform data is shown in 2.4-inch TFT LCD screen. Successful implementation of the
full_adder_VHDLproject
- 常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本文件是全加器模块 1.算术逻辑单元（alu_1706）,实现算术逻辑运算 2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。 3.全加器（full_adder） 4.半加器（half_adder） 5.3-8译码器（mutex_3to8） 6.计算机运算器（S6）实现运算器相关功能-VHDL modules
xilinx_flash
- xilinx flash 开发，实测可用-xilinx flash development, available
SPI_system
- This a SPI for DE_2 board.The file sampling frequency is 20Khz and board frequency used by this 27Mhz.The slaver chip is MCP2302 working under 3.3V.Finally the input analogue voltage for CH0 is between 0V and 3.3V -This is a SPI for DE_2 board.The fi
example17
- 这是一个基于NIOS II的波形产生器的设计其用到了一些DA ,AD内容希望对大家有用-It s a code for wave genenater
reactiontimer
- 初始状态为待命，数码管熄屏。 按按钮到下一个状态，数码管显示倒计时 倒计时之后等待一段时间led灯亮起，按下按钮后显示反应时间，然后等待一段时间后返回等待状态。(1. Idle, which is the default state, is not responding to the test being executed. 2. This will inform users that a new reaction test is about to start. For example,
iic
- iic实现对lm75a的访问。包括对寄存器的读和写操作-To achieve the iic lm751a visit. Including of register of reading and writing
CX25836_7
- Single-Chip Video Decoder
带FIFO的ov7670 FPGA应用程序，经测试可用
- 这是用Verilog编写的OV7670摄像头驱动代码，带FIFO，经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)