资源列表
RCA
- ripple carry adder vhdl code
testbench
- testbench for Carry look ahead adder
Verilog
- 这是 夏宇闻Verilog数字系统设计教程中部分例程代码，适合初学Verilog的人-This is Xia Yu smell Verilog digital system design tutorial part of the routine code, suitable for beginners of Verilog
DataPath
- datapath-datapath of Cpu
DDS
- DDS函数信号发生器，这是我在xilinx平台上实现的，可以产生不同频率，不同函数形式的函数信号。如三角波，方波等-DDS function generator, this is my on xilinx platform, can produce the function of different frequency signals.
serial-and-parallel-convert
- 8bit串行数据转换为8bit并行数据，8bit并行数据转换为8bit串行数据，代码注释完整。-serial and parallel convert
scr
- 八路抢答器，包括按键检测，计时，LED显示，蜂鸣器驱动。-8—way responder
135-classic-Verilog-design-example
- Verilog的135个经典设计实例，移位寄存器，串并转换，交通灯控制等-135 classic Verilog design example, the shift register, string and conversion, traffic light control, etc.
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
clockdiv
- Clock division implementation on verilog VHDL
Sunhaibo
- ＰＣＩ9054的读写，其中包括双口ＲＡＭ，以及寄存器的使用-PCI9054 read and write, which includes dual port RAM, as well as the use of registers
M_UartRecv0
- rs232串口基于VHDL的代码 很有用的 正确的 rs232串口基于VHDL的代码 很有用的 正确的-RS232 serial port based on VHDL code is very useful for the correct RS232 serial port based on VHDL code is very useful