资源列表
sch
- 电子系统设计高层次综合high level synthesis 源码,C++ 实现调度-electronic system level HLS design, cpp code for scheduling
Catapult_HLS-by-C
- 电子系统设计高层次综合high level synthesis工具 Catapult使用及利用C++进行算法开发讲解文档-document about Catapult (HLS tool)using c++ for designing
Exercising-H.264-Video-Compression-IP-Using-Comme
- This book describe about Exercising-H.264-Video-Compression-IP-Using-Commer.
MTM_UEC1_lab04_raportfinalny
- verilog hdl BCD to 7seg converter with testing module
uart_mm
- Its uart transmitter and receiver
SDRAM controller
- This SDRAM controller is useful for SDR_SDRAM IC's can be integrated with the verilog code. The code is developed for the altera FPGA's and it can be ported to other FPGA's easily. The code is verified with terasic DE2-115 board and DE2 boards.
Piano_vhdl
- Here is the Piano code for FPGA(Basys 2) with switches.
dwn_sampler
- Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of
transmitter
- UART transmitter.v.zip
traffic
- 用Verilog语言模拟交通灯实验，内容简单，适合初学者，- Simulation of traffic light experiment using Verilog language
TIMER
- 用Verilog语言模拟的数字时钟的功能，时分秒工能都有，适合做毕设，完整工程-Verilog language simulation of the digital clock function, the time of the second division of the work can be, for the completion of the project, complete
8bits
- 用Verilog语言模拟的8位优先编码器，可作为课堂作业实用，是完整工程代码-Using Verilog language simulation of the 8 priority encoder, can be used as a classroom operation, is a complete code