资源列表
i2cBUS
- Altera的I2C总线FPGA程序，内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source
IO
- 基于NEXYS4 和ISE14.7开发的并行IO接口设计，达到数码管滚动显示数字的功能-NEXYS4 and ISE14.7 developed parallel IO interface based, to the digital display digital scroll function
e1
- 清华大学电子系 组合逻辑实验 包括多路选择器设计，译码器设计，4位加法器设计-Tsinghua University, Department of Electronics, combinational logic experimental design includes multiplexer, decoder design, four adder design
s5
- 清华大学电子系 时序逻辑实验报告 包括：触发器设计，计数器设计，累加器设计，序列检测器设计/有限状态机实现-Tsinghua University, Department of Electronics, sequential logic test report include: trigger design, counter design, accumulator design, the sequence detector design/finite state machine
e8
- 清华大学电子系 数字钟设计实验报告（第8个实验）-Tsinghua University, Department of Electronics, digital clock design lab report (Article 8 experiments)
e10
- 清华大学电子工程系 帧同步器设计实验报告 起始状态定为失步态，通过帧同步码来判断帧的正确性。判断正确则进入预同步态。然后再连续判断两次帧同步码，正确则进入同步态。如果随后的帧的帧头是错误的，则进入保持态以防误码造成的错误。只有在连续发现三次帧头错误才返回失步态。-Electronic Engineering, Tsinghua University, frame synchronizer design experiments starting status report as loss of
e12HDB3
- 清华大学电子工程系 HDB3实验报告 包括：M序列发生器，编码器，解码器-Electronic Engineering, Tsinghua University HDB3 lab report include: M sequence generator, encoders, decoders
ug871_vivad_HLS_tutorial
- Xilinx Vivado HLS 高层次综合工具的软件使用说明-Vivado HLS Xilinx high level integrated tool for the use of software instructions
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
absolute2relative_coding
- ISE编程仿真DPSK中相对码和绝对码的转换-DPSK code conversion relative and absolute code
squa
- Verilog语言ISE下实现方波产生和占空比调节-ISE Verilog language implementations under wave generator
counter6display
- ISE环境下Verilog变成实现六位计数器并用7段显像管显示-ISE Verilog environment becomes realized under six counter with 7-segment display CRT