资源列表
compare
- 用verilog实现文件输入的比较器，如果同一时间输入的数据相同则输出高电平，否则输出低电平，达到比对的效果。-Use verilog implementation file input comparator, if the input data at the same time the same output high level, otherwise the output low level, to achieve the effect of alignment.
changewin
- 用verilog实现40比特的串并转换，激励文件同时写在程序中。-Use verilog implementation 40 bits of string and transform, incentive documents written in a program at the same time.
ELECTRONICCLOCK
- VHDL语言设计的电子钟，并且有暂停功能和清零功能的按键实现，并且带秒表-VHDL language design electronic clock, and there is a pause function and achieve clear function buttons, and with stopwatch
sixty_test1
- 模六十计数器，在basys2实验板上选择右边两个数码管计数，从0到59.依次加一。-count sixty
cpu3
- 简易CPU可执行8条简单指令,如：add,xor,and等-risc cpu
Source_Code
- Xilinx的IP核源码例化，可实现分频和倍频处理，亲测成功-Xilinx instantiated IP core source code, which can realize frequency and frequency doubling processing, measuring success
18_uart
- FPGA的串口程序,有串口控制器，串口发送，串口接收模块和顶层测试 模块等。-verilog code about the FPGA uart module.
FSM
- Verilog编写的FPGA有限状态机一段式描述。-The FSM of FPGA based on Verilog.
lcd1602
- FPGA VHDL LCD1602驱动，已验证-FPGA VHDL LCD1602 driver, verified
fpga calculate
- 基于FPGA的建议运算器，可以实现加、减、乘等算术运算，通过开发板输入输出
fpga usb
- 基于fpga的usb端口verilog调试程序,可利用键盘鼠标控制开发板的一些动作
timer
- 使用Verilog编程的秒表，使用basys2板子，同时支持两个秒表计时，有暂停复位功能，计时在七段数码管上显示。-Using Verilog programming stopwatch, use basys2 board, while supporting the two stopwatch with pause reset function, time on the seven-segment LED display.