资源列表
AES_core
- 蓝牙AES编码，希望对深入了解蓝牙开发的人有帮助-Bluetooth AES coding, and I hope people understand Bluetooth development help
dds
- 这是一个基于ＦＰＧＡ设计的ＤＤＳ信号发生器设计。能够生成正弦波＼ＡＳＫ＼ＰＳＫ＼ＡＭ＼ＦＭ等波形。-This is an FPGA design of DDS signal generator based on. Capable of generating sine \ASK\PSK\AM\FM and other waveforms.
Lcd_800_480
- 基于DE2-70开发板的FPGA和NIOS系统设计的LCD（800-480）液晶显示控制系统的程序设计。-DE2-70 FPGA-based development board and the NIOS system design LCD (800-480) LCD control system programming.
rapport_vhdl
- Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone -Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone II
L-CLA20_20-code.
- DHL CLA20_20 development with the Verilog bit ahead carry adder code.
tp-vhdl
- compteur digital VHDL 1ERE VERSION
Uart_to_bus
- The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. The parser supports two modes of operation: text mode commands and binary mode commands. Text mode commands are designed to be used wi
uart_loopback
- uart loopback and test bench .
DDS_hzh
- 基于FPGA实现的DDS信号发生器，能产生正弦波、方波、锯齿波三种波形。-FPGA-based realization of DDS signal generator can produce sine, square, ramp three waveforms.
DDDDDDDDDSSS
- FPGA实现DDS正弦波、方波、三角波发生器Verilog程序（已验证）Quartus工程文件-FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files
tugedafinal
- 使用Verilog HDL语言写的关于实现对ADC、MDC控制的程序，个人使用Quartus 7.2,在上面进行过仿真，暂时还没有发现问题-Using Verilog HDL language written on the realization of the ADC, MDC control procedures, personal use Quartus 7.2, in the above simulation carried out have had no problems found
ML605_LED
- ML605_LED 用Verilog HDL编写的LED闪烁的程序，很简单-ML605 LCD Verilog HDL prepared with flashing LED program, very simple