资源列表
UART0_2
- vlsi UART referene, use UART0_3
QuartusII
- 在quartus2中实现过的VHDL源码。已经试用过。-Medium quartus2 at implementation of the VHDL source code too. Have tried them already.
VHDL-count
- 这是一种描述加法器的VHDL描述。已经试用过。-This is a descr iption of the VHDL descr iption of adder. Have tried them already.
cam
- 这是使用 fpga实现CAM功能的介绍。用VHDL语言实现。-This is the use of the use of FPGA implementation introduce CAM function. Implementation using VHDL language.
fpgaserialread
- fpga的串口编程vi控件库，提供了多种vi-FPGA serial programming vi Control Library
051203055
- 2位加法器，非常基础有用的哦 加油 支持 顶 很实用的常用的-ADD2
frenquenter
- 等精度频率计设计与文档，有源码，doc格式-Precision frequency meter, etc. The design and documentation, has source code, doc format
f6lift
- 不同于网上的四层电梯，这是六层电梯的模拟程序，也是现在学校要求的，vhdl语言开发，在板子上运行良好-vhdl 6 lift
veriloghdl_teaching_model
- Verilog HDL权威教程，建模实例及语法参考和其他论题- Authority Verilog HDL tutorials , modeling examples and reference grammar ，other topics.
vhdl_manygoodmodel
- VHDL例程集锦，有很多例子，从简单的逻辑例程到复杂的微操作系统和相关存储器。-This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinationa
fulladder
- 使用Vhdl语言实现数字电路全加器功能，算法比较简单，供初学者参考。-full adder
clock
- vhdl 电子钟 计时 上下午 整点报时-VHDL Electronics afternoon bell time on the whole point timekeeping